AFRL - Fielding the Fastest Embeddable Computer in the Air Force
by Virginia Ross, AFRL - Rome Research Site
Our Mission: Leading the discovery, development, and integration of affordable, warfighting technologies for our aerospace forces.
The Air Force Research Laboratory in Rome, New York is purchasing a rugged COTS High Performance Computer (HPC) system from SKYComputers of Chelmsford, Massachusetts. A unique attribute of this ruggedized HPC is its availability to DoD RDT&E organizations and their contractors to accelerate the transition of new HPC applications to field use. Some potential uses include: advanced signal and image processing research in sensor and information fusion, synthetic aperture radar, space-time adaptive processing, automatic target recognition, wavelet-based compression, and hyper-spectral imaging. This system is the fastest embeddable computer in the U.S. Air Force. It was funded through the DoDís High Performance Computing Modernization Program (HPCMP), representing the first purchase of a rugged HPC system by the program.
The configuration being purchased by AFRL includes 384 processors in three chassis and is capable of computer performance of 640 GFLOPS. This SKYchannel System is modular and can easily be reconfigured into three separate computers for phased deployment to the field, with a maximum of 554 GFLOPS for a single chassis.
The compute power of AFRLís new system is derived from 24 PowerPC-based SKYchannel 9U boards combined with the SKYchannel crossbar switching fabric and system software to deliver excellent performance on key benchmarks for signal and image processing. This SKYchannel system is a general-purpose system with a distributed memory architecture.
The design of the memory, communication, and I/O subsystems was optimized for operating on vectors and matrices of data, such as those found in signal and image processing applications.
The SKYchannel System includes system software, development tools, and run-time libraries to support real-time signal and image processing. Foremost among these are advanced compilers and libraries that automatically vectorize application software without depending on code or function parameters tuned for a particular processor or system architecture. With no requirement to learn the processor architecture and then code that into the application, an applications developer can focus on the algorithms while reducing the time to develop, debug, and field test the system.
AFRL accepted and began providing tri-service access to one chassis of the system in June 2000. AFRL is currently testing a second chassis configured with nine boards full of PPC 7400 processors with a peak rating in excess of 450 GFLOPS. This chassis is expected to be ready for development and field testing by the end of September 2000. The third chassis is expected to remain at AFRL to support development activities leading up to field tests. Boards can be easily moved between chassis to support experimental requirements. DoD researchers are encouraged to get accounts and experiment with the system. Contact Virginia Ross for system access and test information and to discuss opportunities for field tests.
Author Contact Information
Virginia Ross
Air Force Research Laboratory/IFTC
26 Electronic Parkway
Rome, NY 13441
(315) 330-4384
Fax: (315) 330-2953
[email protected]
|
System Performance |
| Peak Floating-Point Performance |
640 GFLOPS |
| Peak Bisectional Bandwidth |
1.92 GBytes/sec |
| Total System Memory |
26 GBytes |
|
|
System Configuration Flexibility |
| Each of three systems racks operate
independently, and may be physically disconnected from the others. Any
or all three 9U SKYchannel chassis may be removed from the systems racks
and deployed independently. |
|
|
System Configuration |
| Signal Processors |
(144) PowerPC 7400 and
(240) PowerPC 604e Å 333 MHz processors, each running an 83.3 MHz
memory interface |
| I/O Processors |
(24) Intel i960CA processors |
| Signal Processor Boards |
(24) 9U VME SKYchannel
boards, each with (16) Signal Processors, (1) I/O processor, 1 GByte
memory, (1) FPDP parallel port, and (1) SKYchannel communication port
|
| System Area Network |
(8) SKYchannel Backplanes and
(2) SKYchannel Chassis Hubs, each using SKYchannel Crossbars for
multiple 320 MB/sec connections |
| Additional I/O Interfaces |
(9) Fibre Channel Interfaces
(4) HIPPI Interfaces (1) ATM-OC3 Interface |
| Processor Chassis |
(3) 9U SKYchannel Chassis,
each with (8) Signal Processor boards, (1) UltraSPARC host processor
board, and standard peripherals (CD, HD, Tape) |
| RAID Systems |
(3) 50 GByte RAID level
5 subsystems (1) 144 GByte RAID level 5 subsystem |
| System Racks |
(3) System Racks, each with
(1) 9U SKYchannel Chassis, (1) RAID System. Two racks have (1)
SKYchannel Chassis Hub each. |
| System Expandability |
System may be expanded
without changing the configuration by adding processor boards to
spare slots, up to 16 SKYchannel boards per chassis, and/or by
adding another processor chassis. |
|
Software Development and Run-Time System |
| Host Operating System |
Solaris 2.7 |
| Compilers |
Automatic Vectorizing SKYvec
C/C++ and SKYvec Fortran |
| Signal Processing OS |
SKYmpx Real-Time OS |
| Communications Libraries |
SKYscl Scalable
Communications Library MPI/RT |
| Signal Processing Libraries |
SKYvec SML, VSIP (Vector,
Signal, and Image Processing) Library |
| Real-Time Development |
TimeScan Multiprocessor
Event Analyzer |
